1. Field of the Invention
The invention generally relates to a semiconductor structure. More particularly, the invention relates to a structure with an insulating cap layer.
2. Description of the Prior Art
In the field of semiconductor manufacturing, after a transistor structure is formed, conductive contact plugs are formed to make the transistor fully functional. Source/drain contact (S/D contact) plugs connect to the source and drain region of the transistor, and gate contact plugs connect to the gate of the transistor.
With the continuous scaling down of chip size, the critical dimension (CD) and spacing of these contact plugs is becoming smaller. Conventional contact forming processes have frequently been found to cause issues such as electric shorting between the gate and an S/D contact of a transistor, as well as high contact resistivity resulting from the smaller CD and smaller landing area of the gate contact plug. Those problems may cause failure of the device.
To solve the above issues, self-aligned contact (SAC) (also known as borderless contact technology) has been developed. By disposing an insulating cap layer on the gate to act as a hard mask during the S/D contact hole etching process, the gate electrode will not be etched and exposed, and the short between the S/D contact plug and the gate electrode can thereby be prevented.
The insulating cap layer is not desirable for the gate contact plug, however, as it may cause extra difficulty for the gate contact hole etching. Therefore, there is still a need to provide an improved semiconductor structure, which not only prevents the short between the S/D contact plug and the gate, but also has lower contact resistivity.